The present invention generally relates to semiconductor transistor devices such as MOS SOI transistors, and relates more particularly to a device structure and method of manufacture in which the transistor uses extension region implants as source/drain regions to form ultra shallow junctions, and can employ a two silicide process to reduce contact resistance associated with the transistor and reduce the floating-body-effect for SOI devices.
Transistor devices make up one of the integral components of today""s integrated circuits. Consequently, a reduction in the size of transistors (often called xe2x80x9cscalingxe2x80x9d) is constantly being pursued. Prior art FIG. 1 is a fragmentary cross section diagram illustrating a conventional MOS type transistor 10. The transistor 10 consists of a conductive gate region 12 overlying a thin gate oxide 14 which overlies a substrate 16. The gate 12 and the gate oxide 14 are disposed between a drain region 18 and a source region 20 which are formed in the substrate 16 having a channel region 22 located therebetween which underlies the gate 12 and the gate oxide 14.
As the conventional transistor 10 is scaled into the sub-micron range to reduce its dimensions and thereby improve the transistor packing density on a chip, the transistor 10 begins to experience hot-carrier effects, as illustrated in prior art FIG. 2. These undesirable hot-carrier effects become more evident when the transistor 10 is scaled while maintaining the supply voltage constant or when the supply voltage is not reduced as rapidly as the structural features of the transistor.
The hot-carrier effects are due, at least in part, to an increase in the electrical field within the channel region 22. The increased electric field causes electrons in an inversion layer 26 to be accelerated (or xe2x80x9cheatedxe2x80x9d) to an extent that several different undesirable phenomena occur. As illustrated in prior art FIG. 2, the hot-carrier effects can include charge injection, substrate current and electron injection into the gate oxide 14. Perhaps the most crucial hot-carrier effect is the charge injection into the gate oxide 14 which damages the thin oxide and leads to a time-dependent degradation of various transistor characteristics such as the threshold voltage (VT), the linear transconductance (gm) and the saturation current (IDSAT).
One prior art solution which reduces the undesired hot-carrier effects of traditional transistor structures is the lightly doped drain (LDD) transistor 30, which is illustrated in prior art FIG. 3. The LDD transistor 30 includes the gate 12 and the gate oxide 14 formed in a conventional manner, wherein a lightly doped extension region 32 is formed between the drain region 18 and the channel 22 and the source region 20 and channel, respectively. The lightly doped extension regions 32 typically reduce the electric field near the channel region 22 by about 30-40 percent and thus the hot-carrier reliability of the transistor is greatly improved. The extension regions 32 reduce the electric field by effectively dropping a portion of the drain voltage across the extension region 32.
As transistor designers continue to scale down the transistor device dimensions, the junction depths of the source and drain regions (as well as the lightly doped drain extension region) also need to be reduced (i.e., make the junctions more shallow). Junction depths must be reduced in conjunction with scaling in order to prevent short channel transistor effects such as punchthrough and threshold voltage shift. One conventional approach to reducing the junction depth is to reduce the implant energy used to form the junctions and reduce the diffusion of the junctions in the vertical direction. At the same time, in order to maintain a reasonably low extension region resistance, the dopant concentration must be increased. Such an increase, however, negatively leads to greater diffusion which negatively impacts the shallow nature of the junction. Therefore there is a need in the art to make ultra-shallow junctions without negatively impacting the junction resistance.
In addition to the above issues, the switching speed of a transistor is an important characteristic since it dictates, at least in one respect, how fast the circuits which employ such devices operate. Presently, the switching speed of a transistor is not limited by the channel transit time (i.e., the time required for charge to be transported across the channel); instead, the switching speed is limited by the time required to charge and discharge the capacitances that exist between the device electrodes and between the interconnecting conductive lines and the substrate.
One way of appreciating the transistor capacitances is through an exemplary transistor cross section, as illustrated in prior art FIG. 4. The NMOS transistor, designated at reference numeral 50, includes a p-type region 52 (sometimes referred to as the body), such as a P-well in a CMOS type process. The body 52 has an n-type drain region 54 formed therein and a lightly doped extension region 56. Likewise, a source region 58 and a lightly doped extension region 56 is formed in the body 52. A doped polysilicon gate 72 overlies a thin gate oxide 74 which defines a channel region 76 therebeneath in the body 52.
An effective circuit diagram illustrating the various transistor capacitances is illustrated in prior art FIG. 5. As seen in FIG. 5, capacitances exist between the various device electrodes and between the electrodes and the body region. The drain-to-body capacitance (Cdb) and the source-to-body capacitance (Csb) often are referred to as junction capacitances. The value of the junction capacitances are a function of both the cross sectional area of the junctions as well as the doping concentrations of the regions, respectively.
One attempt to increase the performance of the transistor 50 of prior art FIG. 4 reduces the junction capacitances by forming the transistor on an insulating region. Such a transistor device structure is called a silicon-on-insulator (SOI) device and is illustrated in prior art FIG. 6. The SOI transistor, designated at reference numeral 80, has components similar to the transistor 50 of prior art FIG. 4. In the SOI transistor 80, however, the body 52 is not formed in the bulk semiconductor material as in FIG. 1, but rather overlies an insulating layer 82 such as silicon dioxide (SiO2) and is often called a buried oxide (or BOX). The insulating layer 82, in turn, overlies a bulk semiconductor material 84.
The SOI transistor 80 provides several performance advantages over traditional bulk transistor devices. Initially, since each device can be completely isolated from one another (as opposed to sharing a common body), better individual device isolation is achieved, which prevents circuit latch-up conditions. In addition, since at least a portion of the drain region 54 and the source region 58 abut the insulating layer 84, the cross sectional area of the source/body and drain/body interfaces is reduced and thus the junction capacitance is significantly reduced.
Although SOI devices provide several advantages over prior art bulk type devices, an SOI transistor also has several disadvantages. One disadvantage of SOI transistors could be (depending upon the application) the lack of bulk silicon or body contact to the transistor. In some cases it is desirable to connect the SOI body region 52 to a fixed potential in order to avoid xe2x80x9cfloating-body-effects.xe2x80x9d Use of a body contact for each transistor device, however, undesirably increases the device size and thus is not an amenable solution.
The floating-body-effects refer generally to various hysteresis effects which are associated with the body 52 being allowed to float relative to ground. Two such floating-body-effects include the xe2x80x9ckinkxe2x80x9d effect and the parasitic lateral bipolar effect. The xe2x80x9ckinkxe2x80x9d effect originates from impact ionization. When the SOI transistor 80 is operated at a relatively high drain-to-source voltage, channel electrons having sufficient kinetic energy cause an ionizing collision with the lattice, resulting in carrier multiplication near the drain end of the channel. The generated holes build up in the body 52 of the device 80, thereby raising the body potential. The increased body potential reduces the threshold voltage of the transistor 80, thus increasing the transistor current, which results in a xe2x80x9ckinkxe2x80x9d in the transistor current/voltage (I/V) curves.
The second floating-body-effect includes the parasitic lateral bipolar effect. As discussed above, if impact ionization generates a large number of holes, the body bias may be raised to a sufficient voltage so that the source/body p-n junction becomes forward biased. When this junction becomes forward biased, minority carriers are emitted into the body 52 which causes a parasitic lateral NPN bipolar transistor to turn on. Such parasitic transistor action leads to a loss of gate control of the transistor current and is therefore highly undesirable.
Therefore there is a need in the art for a device and method of manufacture for providing transistor devices having lower resistance and reduced junction capacitance without altering the fundamentals of the device operation.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method of forming a transistor and a transistor structure. The method and structure provide for a device exhibiting a substantial reduction in extension region resistance due to a double silicide process in which a first silicide is formed over the extension regions near a first sidewall spacer formed on lateral edges of a gate structure after the extension region formation. After formation of a second sidewall spacer on lateral edges of a gate structure (covering the first spacers), a second silicide is formed over an exposed portion of the first silicide and on a top portion of the gate structure. In one example, a source/drain implant is performed after the second spacers are formed and prior to the second silicide. Alternatively, the source/drain implant is forgone and the extension regions are employed as ultra-shallow source/drain regions.
In accordance with one aspect of the present invention, a method of forming a transistor comprises forming a gate structure over a semiconductor substrate. First sidewall spacers are formed on lateral edges of the gate structure and an extension region implant is performed either before or after the first sidewall spacer formation. A first metal layer is deposited over the substrate and is subjected to thermal processing to form a first silicide over the extension regions. In one example, a first silicide is also formed over a top portion of the gate structure, while in another example, such silicidation is avoided by maintaining an insulative mask structure over the top portion bf the gate after the patterning thereof.
The method further comprises forming second sidewall spacers on the lateral edges of the gate structure, thereby overlying and covering the first spacers, and performing a source/drain implant through the first silicide in portions of the extension region not covered by the sidewall spacers. A second metal layer is then deposited over the substrate and subjected to thermal processing to form a second silicide over portions of the first silicide not covered by the sidewall spacers and on the top portion of the gate structure. The double silicide process allows for a substantial reduction in extension region resistance and provides other benefits as will be discussed later in greater detail.
In yet another aspect of the present invention, the traditional deep source/drain implant is eliminated and an extension region implant is employed to form ultra-shallow source/drain regions. The method employs a double silicide process and comprises forming a gate structure over a semiconductor substrate. First sidewall spacers are formed on lateral edges of the gate structure and an extension region implant is performed either before or after the first sidewall spacer formation to form source/drain regions. A first metal layer is deposited over the substrate and is subjected to thermal processing to form a first silicide over the source/drain regions. In one example, a first silicide is also formed over a top portion of the gate structure, while in another example, such silicidation is avoided by maintaining an insulative mask structure over the top portion of the gate after the patterning thereof.
The method further comprises forming second sidewall spacers on the lateral edges of the gate structure, thereby overlying and covering the first spacers. A second metal layer is then deposited over the substrate and subjected to thermal processing to form a second silicide over portions of the first silicide not covered by the sidewall spacers and on the top portion of the gate structure. The double silicide process allows for a substantial reduction in source/drain region resistance and allows for ultra-shallow source/drain regions by allowing such regions to be formed using extension region implants.
In accordance with still another aspect of the present invention, a MOS transistor structure is disclosed. The transistor comprises a gate structure overlying a semiconductor substrate with extension regions formed in the substrate on opposite sides thereof, thereby defining a channel region therebetween. First sidewall spacers reside on lateral edges of the gate structure and a first silicide overlies portions of the extension regions. The first silicide regions extend into the extension regions to a depth which is less than a depth of the extension regions and substantially abut the first sidewall spacers. Second sidewall spacers reside on the lateral edges of the gate structure and cover the first spacers. The second silicide regions overlie remaining outside portions of the extension regions and extend into the source/drain regions to a depth which is greater than the first silicide regions. The second silicide regions substantially abut the second sidewall spacers. The double silicide structure allows for reduced extension region resistance and provides various other advantages as will be described later in greater detail.